The present invention relates generally to the field of code division multiple access (CDMA) communication systems, and more particularly to chip timing estimation techniques for use in such systems.
The term xe2x80x9cchipxe2x80x9d in a CDMA system refers generally to a code symbol, that is, a symbol that has been subject to the application of one or more pseudorandom spreading codes. The spreading factor M in a given system is given by T/Tc, where T denotes the original symbol duration and Tc denotes the chip duration. The chip duration is also commonly referred to as the chip interval.
A given chip timing estimation technique generally includes an initial signal acquisition phase followed by a signal tracking phase. The initial acquisition phase typically relies on coarse estimation of the chip timing, with fine estimation being provided by the tracking phase.
Accurate chip timing is particularly critical to the successful operation of recently-developed high-speed CDMA systems such as the 3rd Generation Partnership Project (3GPP) Wideband CDMA (WCDMA) system, described in 3GPP Technical Specifications TS 25.1xx (including, e.g., 25.101, 25.211, 25.212, 25.213, etc.), which are incorporated by reference herein.
In a CDMA system, inaccurate chip timing results in performance loss because code orthogonality lowers the energy of misaligned signals. In addition, when multipath effects are present in such a system, the different path delays need to be determined accurately in order to align and constructively combine the received signal energies in the multiple paths, e.g., using a conventional Rake receiver. More particularly, for each of the path arrival times, chip timing at the transmitter and receiver needs to be well aligned so as to permit correct reconstruction of the data. If the timing mismatch is sufficiently large, the orthogonality of the codes can cause the received signal to appear as noise.
A number of well-known conventional timing estimation techniques are described in J. G. Proakis, xe2x80x9cDigital Communications,xe2x80x9d 3rd Edition, McGraw-Hill, 1995, (e.g., pp. 358-364 and 744-752), which is incorporated by reference herein. These include techniques based on an early-late synchronizer, and techniques based on a delay-locked loop (DLL).
Another conventional technique is described in R. De Gaudenzi, M. Luise and R. Viola, xe2x80x9cA Digital Chip Timing Recovery Loop for Band-Limited Direct-Sequence Spread-Spectrum Signals,xe2x80x9d IEEE Trans. On Communications, Vol. 41, No. 11, pp. 1760-1769, Nov. 1993, which is incorporated by reference herein.
As indicated previously, the goal of the timing estimation techniques noted above is to maintain alignment between transmitter and receiver chip timing. Typically, it is desirable to maintain the timing alignment within about xe2x85x9 of the chip duration Tc for negligible impact on system performance.
Unfortunately, the known chip timing estimation techniques described above may have difficulty maintaining the desired timing alignment in certain systems, or may exhibit other drawbacks such as undue circuit complexity. This is particularly true in the case of high-speed CDMA systems such as the 3GPP WCDMA system. A need therefore exists for improved chip timing estimation techniques for use in such systems.
The present invention provides methods and apparatus for block-based chip timing estimation in a receiver of a CDMA system.
In accordance with one aspect of the invention, a chip timing estimate is generated in the receiver from samples of a received signal by performing an averaging operation over a designated block of chips in each of first and second legs of an early-late synchronizer. The chip timing estimate is determined as a function of an error signal corresponding to the difference between outputs of the first and second legs, and is utilized to adjust a code generator clock or to otherwise control chip timing in the receiver. The chip timing estimate may comprise a further refinement of a coarse chip timing estimate generated for the receiver within an accuracy of a single chip duration.
For example, the chip timing estimate may comprise an estimate of chip timing error normalized to the chip duration Tc.
In an illustrative embodiment, a separate block-based chip timing estimator is implemented in each of the fingers of a Rake receiver. More particularly, chip timing estimates are generated and utilized independently in each of the Rake fingers.
The chip timing estimate may be generated from samples of the received signal by performing a given averaging operation over a specified number Nc of chips in the first leg of the early-late synchronizer and performing the same averaging operation over the same specified number Nc of chips in the second leg. The specified number Nc of chips may be on the order of, e.g., approximately 32 to 64 chips, and may be substantially less than a number of chips Nb which defines an estimation interval for which the chip timing estimate is generated. For example, Nb may be given approximately by the number of chips per slot in a given frame of data, or 2,560 chips in the 3GPP WCDMA system noted above. Other values of N, can be used, e.g., it may be desirable to use more than 64 chips in particularly noisy conditions.
The invention in the illustrative embodiment is configured such that the chip timing estimate is determined in an open-loop, feed-forward manner. The invention thus provides an improved chip timing estimator which eliminates the need for a hardware-based timing loop, and can therefore be implemented primarily in the form of software. This arrangement advantageously provides improved performance in the 3GPP WCDMA system and other high-speed CDMA systems, while also reducing the cost and complexity of the receiver circuitry.